Design and Realization of FIR Filter for Inter Satellite Link at 50-90 MHZ Frequency using FPGA
DOI:
https://doi.org/10.14203/jet.v16.15-19Keywords:
FIR filter, equiripple, FPGA, VHDLAbstract
In this paper, design and realization of FIR filter with a bandwidth of 40 MHz at 50-90 MHz frequency has been proposed. The design was destined to be implemented on the Inter Satellite Links (ISL). This kind of filter had been selected due to a need in linear phase responseon the ISL data communication. Equiripple method was used to design the filter becauseof its reliability in minimizing the magnitude errors. The design of this FIR filter was conducted with theoretical calculation and simulation using the R2012b Matlab. For the implementation, FPGA was used with a VHDL as the programming language with a help of Xilinx ISE Design Suite 14.5. Simulation results in Matlab and Simulink indicated that the filter design could be well implemented on ISL at frequency of 50 MHz - 90 MHz with stopband of 60 db. The phase responseresult of the realized design is quite linear so that the filter is suitable for data communication on the ISL.
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